CY7C1484BV25 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

CY7C1484BV25
72-Mbit (2 M × 36) Pipelined DCD Sync SRAM
72-Mbit (2 M × 36) Pipelined DCD Sync SRAM
Features
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250 MHz
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double cycle deselect)
■ Depth expansion without wait state
■ 2.5 V core power supply (V_DD)
■ 2.5 V I/O supply (V_DDQ)
■ Fast clock to output times
❐ 3.0 ns (for 250 MHz device)
■ Provide high performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel^® Pentium^®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed writes
■ Asynchronous output enable
■ CY7C1484BV25 available in JEDEC-standard Pb-free 100-pin
TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE₁), depth expansion
Chip Enables (CE₂ and CE₃), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW_X and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle. This part supports byte write
operations (see Pin Definitions on page 5 and Truth Table on
page 8 for more information). Write cycles can be one to four
bytes wide as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written. This device
incorporates an additional pipelined enable register, which
delays turning off the output buffers an additional cycle when a
deselect is executed. This feature allows depth expansion
without penalizing system performance.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
250 MHz Unit
3.0
ns
450
mA
120
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75258 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 27, 2012