CY7C1481BV33 Datasheet, PDF (1/32 Pages) Cypress Semiconductor – 72-Mbit (2 M × 36) Flow-Through SRAM

CY7C1481BV33
72-Mbit (2 M × 36) Flow-Through SRAM
72-Mbit (2 M × 36) Flow-Through SRAM
Features
■ Supports 133 MHz bus operations
■ 2 M × 36 common I/O
■ 3.3 V core power supply (V_DD)
■ 2.5 V or 3.3 V I/O supply (V_DDQ)
■ Fast clock to output time
❐ 6.5 ns (133 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel^® Pentium^®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed write
■ Asynchronous output enable
■ CY7C1481BV33 available in JEDEC standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG compatible boundary scan
■ ZZ sleep mode option
Functional Description
The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow
through SRAM designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive edge triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
Chip Enable (CE₁), depth expansion Chip Enables (CE₂ and
CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW_x and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1481BV33 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1481BV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC standard JESD8-5 compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz Unit
6.5
ns
335
mA
150
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-74857 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 9, 2013