CY7C1480V33 Datasheet, PDF (1/30 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

PRELIMINARY
CY7C1480V33
CY7C1482V33
CY7C1486V33
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined
Sync SRAM
Features
Functional Description^[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200,167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.0 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• CY7C1480V33 and CY7C1482V33 offered in
JEDEC-standard lead-free 100-pin TQFP, 165-Ball fBGA
packages. CY7C1486V33 available in 209-Ball BGA
packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM
integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE₁), depth-expansion Chip Enables (CE₂ and
CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW_X, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates
from a +3.3V core power supply while all outputs may operate
with either a +2.5 or +3.3V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
200 MHz
167 MHz
Unit
3.0
3.0
3.4
ns
500
500
450
mA
120
120
120
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05283 Rev. *C
Revised December 3, 2004