CY7C1471V25_13 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – 72-Mbit (2 M x 36) Flow-Through SRAM with NoBL™ Architecture

CY7C1471V25
72-Mbit (2 M × 36) Flow-Through SRAM
with NoBL™ Architecture
72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states
■ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
■ 2.5 V I/O supply (V_DDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self timed writes
■ Asynchronous output enable (OE)
■ CY7C1471V25 available in JEDEC-standard Pb-free 100-pin
TQFP
■ Three chip enables (CE₁, CE₂, CE₃) for simple depth
expansion.
■ Automatic power-down feature available using ZZ mode or CE
deselect.
■ Burst capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1471V25 are 2.5 V, 2 M × 36 synchronous flow
through burst SRAMs designed specifically to support unlimited
true back-to-back read or write operations without the insertion
of wait states. The CY7C1471V25 are equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive read or write operations with data transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four byte write select
(BW_X) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz Unit
6.5
ns
305
mA
120
mA
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05287 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 24, 2013