CY7C1471BV33_11 Datasheet, PDF (1/35 Pages) Cypress Semiconductor – 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture

CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Flow-Through SRAM with
NoBL™ Architecture
Features
■ No bus latency™ (NoBL™) architecture eliminates dead cycles
between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states
■ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
■ 3.3 V/2.5 V I/O supply (V_DDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable (OE)
■ CY7C1471BV33, CY7C1473BV33 available in
JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP),
Pb-free and non-Pb-free 165-ball fine-pitch ball grid array
(FBGA) package. CY7C1475BV33 available in Pb-free and
non-Pb-free 209-ball FBGA package
■ Three chip enables (CE₁, CE₂, CE₃) for simple depth
expansion
■ Automatic power-down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG boundary scan compatible
■ Burst capability—linear or interleaved burst order
■ Low standby power
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
Functional Description
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are 3.3 V, 2M × 36/4M × 18/1M × 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are equipped with the advanced No Bus
Latency (NoBL) logic. NoBL™ is required to enable consecutive
read or write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by two or four Byte Write Select
(BW_X) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
133 MHz
117 MHz
Unit
6.5
8.5
ns
305
275
mA
120
120
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15029 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 30, 2011
[+] Feedback