CY7C1470V33_13 Datasheet, PDF (1/38 Pages) Cypress Semiconductor – 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL™ Architecture

CY7C1470V33
CY7C1472V33
CY7C1474V33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT
■ Supports 200 MHz Bus operations with zero wait states
❐ Available speed grades are 200 and 167 MHz
■ Internally self timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 3.3 V power supply
■ 3.3 V/2.5 V I/O power supply
■ Fast clock-to-output time
❐ 3.0 ns (for 200 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ CY7C1470V33 available in JEDEC-standard Pb-free 100-pin
TQFP, and non Pb-free 165-ball FBGA package.
CY7C1472V33 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1474V33 available in non Pb-free 209-ball FBGA
package
■ IEEE 1149.1 JTAG boundary scan compatible
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back-to-back
read/write operations with no wait states. The CY7C1470V33,
CY7C1472V33, and CY7C1474V33 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BW_a–BW_h for CY7C1474V33, BW_a–BW_d for CY7C1470V33
and BW_a–BW_b for CY7C1472V33) and a write enable (WE)
input. All writes are conducted with on-chip synchronous self
timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
200 MHz
3.0
500
120
167 MHz Unit
3.4
ns
450
mA
120
mA
Errata: For information on silicon errata, see Errata on page 34. Details include trigger conditions, devices affected, and proposed workaround
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05289 Rev. *S
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 27, 2013