CY7C1470V25_11 Datasheet, PDF (1/31 Pages) Cypress Semiconductor – 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture

CY7C1470V25
CY7C1472V25
CY7C1474V25
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture
Features
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200 and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 2.5 V power supply
■ 2.5 V/1.8 V I/O supply (V_DDQ)
■ Fast clock-to-output times
❐ 3.0 ns (for 250-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ CY7C1470V25, CY7C1472V25 available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and
non Pb-free 165-ball FBGA package. CY7C1474V25 available
in Pb-free and non Pb-free 209-ball FBGA package
■ IEEE 1149.1 JTAG boundary scan compatible
■ Burst capability—linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2
M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations
with
no
wait
states.
The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible
and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BW_a–BW_h for CY7C1474V25, BW_a–BW_d for CY7C1470V25
and BW_a–BW_b for CY7C1472V25) and a write enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Logic Block Diagram - CY7C1470V25 (2 M × 36)
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
S
E
N
S
E
MEMORY
ARRAY
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
DQPa
DQPb
DQPc
DQPd
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05290 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 28, 2011
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