CY7C144AV_12 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 3.3 V 8 K / 16 K × 8 Asynchronous Dual-Port Static RAM

CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM
CY7C144AV
CY7C006AV
3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM
3.3 V 8 K / 16 K × 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 8 K / 16 K × 8 organizations (CY7C144AV/CY7C006AV)
■ 0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
■ High-speed access: 25 ns
■ Low operating power
❐ Active: I_CC = 115 mA (typical)
❐ Standby: I_SB3 = 10 A (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 16 bits or more using Master/ Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Pin select for Master or Slave
■ Available in 64-pin thin quad flat pack (TQFP) (7C006AV and
7C144AV)
■ Pb-free packages available
Logic Block Diagram
R/W_L
CE_L
OE_L
R/W_R
CE_R
OE_R
[1]
8
I/O_0L–I/O_7L
I/O
Control
I/O
Control
8
[1]
I/O_0R–I/O_7R
A_0L–A_{12–1[32L]}
A_0L–A_{12–1[32L]}
CE_L
OE_L
R/W_L
BSUEMSY^L _L[3]
INT_L
13–14
Address
Decode
13–14
True Dual-Ported
RAM Array
Interrupt
Semaphore
Arbitration
M/S
Address
Decode
13–14
13–14
A_0R–A_{12–13R[2]}
A_0R–A_{12–13[R2]}
CE_R
OE_R
R/W_R
SEM_R
BUSY_R[3]
INT_R
Notes
1. I/O₀–I/O₇ for × 8 devices
2. A₀–A₁₂ for 8K devices; A₀–A₁₃ for 16K devices
3. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06051 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 1, 2012