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CY7C144AV Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 3.3V 8K/16K x 8 Dual-Port Static RAM | |||
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CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 8K/16K x 8
Dual-Port Static RAM
Features
â True dual-ported memory cells which allow
simultaneous access of the same memory location
â 8K/16K x 8 organizations
(CY7C144AV/006AV)
â 0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
â High-speed access: 25 ns
â Low operating power
â Active: ICC = 115 mA (typical)
â Standby: ISB3 = 10 ïA (typical)
â Fully asynchronous operation
â Automatic power-down
Logic Block Diagram
R/WL
CEL
OEL
[1]
8
I/O0LâI/O7L
I/O
Control
CY7C144AV
CY7C006AV
3.3V 8K/16K x 8
Dual-Port Static RAM
â Expandable data bus to 16 bits or more using Master/ Slave
chip select when using more than one device
â On-chip arbitration logic
â Semaphores included to permit software handshaking
between ports
â INT flag for port-to-port communication
â Pin select for Master or Slave
â Commercial and industrial temperature ranges
â Available in 64-pin thin quad flat pack (TQFP) (7C006AV &
7C144AV)
â Pb-free packages available
I/O
Control
R/WR
CER
OER
8
[1]
I/O0RâI/O7R
A0LâA[122] â13L
13â14
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
13â14
[2]
A0RâA12â13R
A0LâA[122] â13L
CEL
OEL
R/WL
SEML
BUSYL [3]
INTL
13â14
Notes
1. I/O0âI/O7 for x8 devices
2. A0âA12 for 8K devices; A0âA13 for 16K devices
3. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
13â14
A0RâA1[22]â13R
CER
OER
R/WR
SEMR
[3]BUSYR
INTR
Cypress Semiconductor Corporation ⢠198 Champion Court
Document #: 38-06051 Rev. *E
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised February 4, 2011
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