CY7C1444AV33_10 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM 3.3 V core power supply

CY7C1444AV33
CY7C1445AV33
36-Mbit (1 M × 36/2 M × 18)
Pipelined DCD Sync SRAM
36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Features
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double-cycle deselect)
■ Depth expansion without wait state
■ 3.3 V core power supply
■ 2.5 V/3.3 V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ CY7C1444AV33, CY7C1445AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package and Pb-free
and non Pb-free 165-ball FBGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
Functional Description^[1]
The CY7C1444AV33/CY7C1445AV33 SRAM integrates
1 M × 36/2 M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE₁), depth-expansion chip
enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP, and
ADV), write enables (BW_X, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active _LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
The CY7C1444AV33/CY7C1445AV33 operates from a +3.3 V
core power supply while all outputs operate with a +3.3 V or a
+2.5 V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05352 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 29, 2010
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