CY7C1441AV25_13 Datasheet, PDF (1/33 Pages) Cypress Semiconductor – 36-Mbit (1 M x 36/512 K x 72) Flow-Through SRAM

CY7C1441AV25
CY7C1447AV25
36-Mbit (1 M × 36/512 K × 72)
Flow-Through SRAM
36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM
Features
■ Supports 133 MHz bus operations
■ 1 M × 36/512 K × 72 common I/O
■ 2.5 V core power supply
■ 2.5 V and 1.8 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed write
■ Asynchronous output enable
■ CY7C1441AV25 available in Pb-free 165-ball FBGA package.
CY7C1447AV25 available in non Pb-free 209-ball FBGA
package.
■ JTAG boundary scan for FBGA package
■ ZZ sleep mode option
Functional Description
The
CY7C1441AV25/CY7C1447AV25
are
2.5 V,
1 M × 36/512 K × 72 Synchronous Flow-Through SRAMs,
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE₁), depth expansion
Chip Enables (CE₂ and CE₃), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW_x and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
The CY7C1441AV25/CY7C1447AV25 allows either interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence and a LOW selects
a linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either ADSP or ADSC are active. Subsequent burst
addresses can be internally generated as controlled by the ADV.
The CY7C1441AV25/CY7C1447AV25 operates from a
+2.5 V core power supply while all outputs may operate with
either a +2.5 V or 1.8 V supply. All inputs and outputs are
JEDEC-standard JESD8-5 compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz Unit
6.5
ns
270
mA
120
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75380 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 7, 2013