CY7C144 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
CY7C144
CY7C145
Features
• True Dual-Ported memory cells that allow simultaneous
reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: I_CC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pb-Free packages available
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W L
CE L
OE L
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be utilized as a standalone 64/72-Kbit
dual-port static RAM or multiple devices can be combined in
order to function as a 16/18-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 16/18-bit
or wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
R/W R
CE R
OER
(7C145) I/O8L
I/O7L
I/O0L
BUSY_L^{[1, 2]}
A 12L
A 0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O 8R(7C145)
I/O 7R
I/O 0R
BUSYR ^{[1, 2]}
A 12R
A 0R
CEL
OEL
R/W L
SEM L
INT L[2]
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CE R
OE R
R/W R
SEM_R
INTR [2]
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06034 Rev. *C
Revised September 6, 2005