CY7C1418KV18_12 Datasheet, PDF (1/31 Pages) Cypress Semiconductor – 36-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1418KV18, CY7C1420KV18
36-Mbit DDR II SRAM Two-Word
Burst Architecture
36-Mbit DDR II SRAM Two-Word Burst Architecture
Features
■ 36-Mbit density (2 M × 18, 1 M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V to V_DD)
❐ Supports both 1.5 V and 1.8 V IO supply
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1418KV18 – 2 M × 18
CY7C1420KV18 – 1 M × 36
Functional Description
The CY7C1418KV18, and CY7C1420KV18 are 1.8 V
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1418KV18 and CY7C1420KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1418KV18 and two 36-bit words in the case of
CY7C1420KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz 250 MHz Unit
333
300
250
MHz
× 18
490
460
430
mA
× 36
600
560
490
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57827 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 22, 2012