CY7C1399D Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 256K (32K x 8) Static RAM

PRELIMINARY
CY7C1399D
256K (32K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C1399B
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— t_AA = 8 ns
• Low active power
— I_CC = 60 mA @ 10 ns
• Low CMOS standby power
— I_SB2 = 1.2 mA (“L” Version only)
• Data Retention at 2.0V
• Available in 28-SOJ and 28-TSOP I Pb-Free packages
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
CE
WE
OE
INPUT BUFFER
32K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Functional Description^[1]
The CY7C1399D is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tri-state drivers. The
device has an automatic power-down feature, reducing the
power consumption when deselected.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O₀ through I/O₇) is written into the memory location
addressed by the address present on the address pins (A₀
through A₁₄). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399D is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I Pb-Free packages.
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Pin Configurations
SOJ
Top View
A₅ 1
A_{6 2}
A₇ 3
A_{8 4}
A_{9 5}
A_{10 6}
A_{11 7}
A_{12 8}
A_{13 9}
A₁₄ 10
I/O₀ 11
I/O₁ 12
I/O₂ 13
GND 14
28 VCC
27 WE
26 A₄
25 A₃
24 _A2
23 _A1
22 _OE
21 A₀
20 CE
19 I/O₇
18 I/O₆
17 I/O₅
16 I/O₄
15 I/O₃
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05467 Rev. *C
Revised January 10, 2005