CY7C1399B Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 32K x 8 3.3V Static RAM

C1399B
CY7C1399B
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— 10/12/15 ns
• Low active power
— 216 mW (max.)
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Functional Description^[1]
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
32K x 8 3.3V Static RAM
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O₀
through I/O₇) is written into the memory location addressed by
the address present on the address pins (A₀ through A₁₄).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
CE
WE
OE
INPUT BUFFER
32K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Pin Configurations
SOJ
Top View
A₅ 1
A_{6 2}
A₇ 3
A_{8 4}
A_{9 5}
A_{10 6}
A_{11 7}
A_{12 8}
A_{13 9}
A₁₄ 10
I/O₀ 11
I/O₁ 12
I/O₂ 13
GND 14
28 VCC
27 WE
26 A₄
25 A₃
24 _A2
23 _A1
22 _OE
21 A₀
20 CE
19 I/O₇
18 I/O₆
17 I/O₅
16 I/O₄
15 I/O₃
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
1399B-10
10
60
500
L
50
1399B-12
12
55
500
50
1399B-15
15
50
500
50
1399B-20
20
45
500
50
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05071 Rev. *C
Revised June 19, 2001