CY7C138_09 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

CY7C138, CY7C139
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
■ True Dual-Ported Memory Cells that Enable Simultaneous
Reads of the Same Memory Location
■ 4K x 8 Organization (CY7C138)
■ 4K x 9 Organization (CY7C139)
■ 0.65-micron CMOS for Optimum Speed and Power
■ High Speed Access: 15 ns
■ Low Operating Power: I_CC = 160 mA (max.)
■ Fully Asynchronous Operation
■ Automatic Power Down
■ TTL Compatible
■ Expandable Data Bus to 32/36 Bits or more using
Master/Slave Chip Select when using more than one
Device
■ On-Chip Arbitration Logic
■ Semaphores Included to Permit Software Handshaking
between Ports
■ INT Flag for Port-to-Port Communication
■ Available in 68-pin PLCC
■ Pb-free Packages Available
Logic Block Diagram
R/W_L
CE_L
OE_L
Functional Description
The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9 can
be used as a standalone 8/9-bit dual-port static RAM or multiple
devices can be combined to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multipro-
cessor designs, communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
R/W_R
CE_R
OE_R
(7C139)I/O_8L
I/O_7L
I/O_0L
BUSY_L^{[1, 2]}
A_11L
A_0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O_8R (7C139)
I/O_7R
I/O_0R
BUSY_R^{[1, 2]}
A_11R
A_0R
SEM_L
INT_L^[2]
CE_L
OE_L
R/W_L
\
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CE_R
OE_R
R/W_R
SEM_R
INT_R[2]
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06037 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 03, 2009
[+] Feedback