CY7C138_05 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
CY7C138
CY7C139
Features
• True Dual-Ported memory cells that allow simultaneous
reads of the same memory location
• 4K x 8 organization (CY7C138)
• 4K x 9 organization (CY7C139)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I_CC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC
• Pb-Free packages available
Functional Description
The CY7C138 and CY7C139 are high-speed CMOS 4K x 8
and 4K x 9 dual-port static RAMs. Various arbitration schemes
Logic BlockDiagram
R/W_L
CE_L
OE_L
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
are included on the CY7C138/9 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C138/9 can be utilized as a standalone 8/9-bit dual-port
static RAM or multiple devices can be combined in order to
function as a 16/18-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 16/18-bit or
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
R/W_R
CE_R
OE_R
(7C139)I/O_8L
I/O_7L
I/O_0L
BUSY_L^{[1, 2]}
A_11L
A_0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O_8R (7C139)
I/O_7R
I/O_0R
BUSY_R^{[1, 2]}
A_11R
A_0R
CE_L
OE_L
R/W_L
SEM_L
INT_L^[2]
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CE_R
OE_R
R/W_R
SEM_R
INT_R[2]
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06037 Rev. *B
Revised September 6, 2005