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CY7C138AV Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM | |||
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CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
Features
⢠True Dual-Ported memory cells which allow
simultaneous access of the same memory location
⢠4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
⢠4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
⢠0.35-micron CMOS for optimum speed/power
⢠High-speed access: 20/25 ns
⢠Low operating power
â Active: ICC = 115 mA (typical)
â Standby: ISB3 = 10 µA (typical)
⢠Fully asynchronous operation
Logic Block Diagram
R/WL
CEL
OEL
[1]
8/9
I/O0LâI/O7/8L
I/O
Control
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
⢠Automatic power-down
⢠Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
⢠On-chip arbitration logic
⢠Semaphores included to permit software handshaking
between ports
⢠INT flag for port-to-port communication
⢠Pin select for Master or Slave
⢠Commercial and Industrial Temperature Ranges
⢠Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
⢠Pb-Free packages available
I/O
Control
R/WR
CER
OER
8/9
[1]
I/O0RâI/O7/8R
[2]
A0LâA11â14L
12â15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
12â15
[2]
A0RâA11â14R
A0LâA[121]â14L
CEL
OEL
R/WL
SEML
BUSYL [3]
INTL
12â15
Interrupt
Semaphore
Arbitration
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. I/O0âI/O7 for x8 devices; I/O0âI/O8 for x9 devices.
2. A0âA11 for 4K devices; A0âA12 for 8K devices; A0âA13 for 16K devices; A0âA14 for 32K devices;
3. BUSY is an output in master mode and an input in slave mode.
12â15
[2]
A0RâA11â14R
CER
OER
R/WR
SEMR
[3]BUSYR
INTR
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose ⢠CA 95134 ⢠408-943-2600
Document #: 38-06051 Rev. *C
Revised June 6, 2005
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