CY7C1386CV25 Datasheet, PDF (1/36 Pages) Cypress Semiconductor – 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

CY7C1386CV25
CY7C1387CV25
18-Mb (512K x 36/1M x 18) Pipelined DCD
Sync SRAM
Features
Functional Description^[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
• 2.5V + 5% power supply (V_DD)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel^
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1386CV25/CY7C1387CV25 SRAM integrates
524,288 x 36 and 1048,576 x 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining
depth-expansion Chip Enables
Control inputs (ADSC, _ADSP, and
Chip
(CE₂
ADV),
Enable
and
Write
ECnEa³b^[2le^])s,
(CBEur_1s)t,
(BW_X,
and _BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. _GW active _LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1386CV25/CY7C1387CV25 operates from a +2.5V
power supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
225 MHz
200 MHz
167 MHz
Maximum Access Time
2.6
2.8
3.0
3.4
Maximum Operating Current
350
325
300
275
Maximum CMOS Standby Current
70
70
70
70
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE₃ and CE₂ are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05242 Rev. *A
Revised February 26, 2004