CY7C1381D_11 Datasheet, PDF (1/34 Pages) Cypress Semiconductor – 18 Mbit (512 K × 36/1 M × 18) Flow Through SRAM

CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
18 Mbit (512 K × 36/1 M × 18)
Flow Through SRAM
18 Mbit (512 K × 36/1 M × 18) Flow Through SRAM
Features
■ Supports 133 MHz bus operations
■ 512 K × 36 and 1 M × 18 common I/O
■ 3.3 V core power supply (V_DD)
■ 2.5 V or 3.3 V I/O supply (V_DDQ)
■ Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■ Provides high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ CY7C1381D/CY7C1381F available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FPBGA package. CY7C1381F/CY7C1383F available in
Pb-free and non Pb-free 119-ball BGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
Functional Description
The CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F is a
3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through
SRAMs, designed to interface with high speed microprocessors
with minimum glue logic^[1]. Maximum access delay from clock
rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures
the first address in a burst and increments the address
automatically for the rest of the burst access. All synchronous
inputs are gated by registers controlled by a positive edge
triggered clock input (CLK). The synchronous inputs include all
daeddprthe-sesxepsa, naslliodnatachinippuetnsa, baldedsre(CssEp₂^{ipaenldiniCnEg} ₃^ch[2ip]),ebnuarbsltec(oCnEtr¹o),l
inputs (ADSC, ADSP, and ADV), write enables (BW_x, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
The CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F allows
interleaved or linear burst sequences, selected by the MODE
input pin. A HIGH selects an interleaved burst sequence, while
a LOW selects a linear burst sequence. Burst accesses can be
initiated with the processor address strobe (ADSP) or the cache
controller address strobe (ADSC) inputs. Address advancement
is controlled by the address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F operates
from a +3.3 V core power supply while all outputs operate with a
+2.5 V or +3.3 V supply. All inputs and outputs are
JEDEC-standard and JESD8-5-compatible.
Notes
1. For best practices or recommendations, refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE_3, CE₂ are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05544 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 3, 2011
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