CY7C1370D_11 Datasheet, PDF (1/33 Pages) Cypress Semiconductor – 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM with NoBL Architecture

CY7C1370D, CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ 3.3 V core power supply (V_DD)
■ 3.3 V/2.5 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 119-ball BGA and 165-ball FBGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability—linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and
1 M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370D and CY7C1372D are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370D and CY7C1372D are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BW_a–BW_d for CY7C1370D and BW_a–BW_b for CY7C1372D)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Logic Block Diagram - CY7C1370D (512 K × 36)
A0, A1, A
MODE
CLK
C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
S
E
N
S
E
MEMORY
ARRAY
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05555 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 8, 2011
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