CY7C1368C Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 9-Mbit (256K x 32) Pipelined DCD Sync SRAM

CY7C1368C
9-Mbit (256K x 32) Pipelined DCD Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 256K × 32-bit common I/O architecture
• 3.3V core power supply (V_DD)
• 2.5V/3.3V I/O power supply (V_DDQ)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Multiple chip enables for depth expansion: Three chip
enables for A package version and Two chip enables
for AJ package version
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
2.8
250
40
Functional Description^[1]
The CY7C1368C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE₁), depth-expansion Chip Enables (CE₂ and CE_3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_A,
BW_B, BW_C, BW_D, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see Pin Descriptions and Truth Table for
further details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active _LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal
izing system performance.
The CY7C1368C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
200 MHz
3.0
220
40
166 MHz
Unit
3.5
ns
180
mA
40
mA
Notes:
1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. CE₃ is for A version (3 Chip enable option) only.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05686 Rev. *F
Revised September 14, 2006
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