CY7C1363D Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 9-Mbit (512 K x 18) Flow-Through SRAM

CY7C1363D
9-Mbit (512 K × 18) Flow-Through SRAM
9-Mbit (512 K × 18) Flow-Through SRAM
Features
■ Supports 133 MHz bus operations
■ 512 K × 18 common I/O
■ 3.3 V – 5% and +10% core power supply (V_DD)
■ 2.5 V or 3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ TQFP available with 3-chip enable
■ “ZZ” sleep mode option
Functional Description
The CY7C1363D is a 3.3 V, 512 K × 18 synchronous flow-through
SRAM, respectively designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
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chip enables (CE₂ and
ADSP, and ADV), write
enables (BW_x, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1363D enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1363D operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Industrial
133 MHz Unit
6.5
ns
250
mA
40
mA
Note
1. CE₃ is for A version of 100-pin TQFP (3 Chip Enable Option).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86215 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 20, 2013