CY7C1361C_2009 Datasheet, PDF (1/32 Pages) Cypress Semiconductor – 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

CY7C1361C/CY7C1363C
9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM
Features
Functional Description
■ Supports 100, 133 MHz Bus Operations
■ Supports 100 MHz Bus Operations (Automotive)
■ 256K × 36/512K × 18 Common I/O
■ 3.3V –5% and +10% Core Power Supply (V_DD)
■ 2.5V or 3.3V I/O Power Supply (V_DDQ)
■ Fast Clock-to-Output Times
❐ 6.5 ns (133-MHz version)
■ Provide High Performance 2-1-1-1 Access Rate
■ User-selectable Burst Counter supporting Intel® Pentium®
Interleaved or Linear Burst Sequences
■ Separate Processor and Controller Address Strobes
■ Synchronous Self-timed Write
■ Asynchronous Output Enable
■ Available in Pb-free 100-Pin TQFP Package, Pb-free and non
Pb-free 119-Ball BGA Package, and 165-Ball FBGA Package
■ TQFP Available with 3-Chip Enable and 2-Chip Enable
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
The CY7C1361C/CY7C1363C^[1] is a 3.3V, 256K x 36/512K x 18
synchronous flow-through SRAMs, respectively designed to
interface with high speed microprocessors with minimum glue
logic. Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in a
burst and increments the address automatically for the rest of the
burst access. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining
Enables (CE₂ and
Chip Enable
CE_3[2]), Burst
(CE₁), depth-expansion Chip
Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW_x, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE) and
the ZZ pin.
The CY7C1361C/CY7C1363C enables either interleaved or
linear burst sequences, selected by the MODE input pin. A HIGH
selects an interleaved burst sequence, while a LOW selects a
linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1361C/CY7C1363C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5 or
+3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Description
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
250
180
mA
Maximum CMOS Standby Current
Commercial/
40
Industrial
40
mA
Automotive
60
mA
Notes
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE₃ is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05541 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 26, 2009
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