CY7C1360C_12 Datasheet, PDF (1/37 Pages) Cypress Semiconductor – 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM

CY7C1360C, CY7C1362C
9-Mbit (256 K × 36/512 K × 18)
Pipelined SRAM
9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM
Features
■ Supports bus operation up to 200 MHz
■ Available speed grades: 200 MHz, and 166 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply (V_DD)
■ 2.5 V/3.3 V I/O operation (V_DDQ)
■ Fast clock-to-output times
❐ 3.0 ns (for 200 MHz device)
■ Provide high performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel^ Pentium^®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Single cycle chip deselect
■ Available in Pb-free 100-pin TQFP package, non Pb-free
119-ball BGA package, and 165-ball FBGA package
■ TQFP available with 3-chip enable and 2-chip enable
■ IEEE 1149.1 JTAG-compatible boundary scan
Functional Description
The CY7C1360C/CY7C1362C SRAM integrates 256 K × 36 and
512 K × 18 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
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chip enables (CE₂ and
ADSP, and ADV), write
enables (BW_X, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 8 and Truth Table on
page 11 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1360C/CY7C1362C operate from a +3.3 V core power
supply while all outputs may operate with either a +2.5 or +3.3 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
200 MHz
3.0
220
40
166 MHz Unit
3.5
ns
180
mA
40
mA
Note
1. CE₃ is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05540 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 25, 2012