CY7C1360A Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

CY7C1360A
CY7C1362A
256K x 36/512K x 18 Synchronous
Pipelined Burst SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225, 200, 166, and 150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V-tolerant inputs except I/Os
• Clamp diodes to V_SS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for A package version and two chip
enables for BG and AJ package versions
• Address pipeline capability
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down feature available using ZZ mode
or CE deselect
• JTAG boundary scan for BG and AJ package version
• Low-profile 119-bump, 14-mm × 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A and CY7C1362A SRAMs integrate 262,144
× 36 and 524,288 × 18 SRAM cells with advanced
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
7C1360A-225
7C1362A-225
2.5
650
10
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), depth-expansion
Chip Enables (CE₂ and CE₃), burst control inputs (ADSC,
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and
BWE), and global Write (GW). However, the CE₃ chip enable
input is only available for the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B and T package versions, four pins are used to
implement JTAG test capabilities: Test Mode Select (TMS),
Test Data-In (TDI), Test Clock (TCK), and Test Data-Out
(TDO). The JTAG circuitry is used to serially shift data to and
from the device. JTAG inputs use LVTTL/LVCMOS levels to
shift data during this testing mode of operation. The TA
package version does not offer the JTAG capability.
The CY7C1360A and CY7C1362A operate from a +3.3V
power supply. All inputs and outputs are LVTTL-compatible.
7C1360A-200
7C1362A-200
3.0
620
10
7C1360A-166
7C1362A-166
3.5
530
10
7C1360A-150
7C1362A-150 Unit
3.5
ns
480
mA
10
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05258 Rev. *A
Revised May 24, 2002