CY7C1354DV25 Datasheet, PDF (1/29 Pages) Cypress Semiconductor – 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

CY7C1354DV25, CY7C1356DV25
9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible with and functionally equivalent to ZBT™
■ Supports 250 MHz bus operations with zero wait states
■ Available speed grades are 250, 200, and 166 MHz
■ Internally self timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ Single 2.5V power supply (V_DD)
■ Fast clock-to-output times
❐ 2.8 ns (for 250 MHz device)
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ Available in Pb-free 100-pin TQFP package, Pb-free and non
Pb-free 119-ball BGA package, and 165-ball FBGA package
■ IEEE 1149.1 JTAG compatible boundary scan
■ Burst capability–linear or interleaved burst order
■ “ZZ” Sleep mode and Stop Clock options
Functional Description
The CY7C1354DV25 and CY7C1356DV25 are 2.5V, 256K x 36
and 512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back to back read and write operations
with no wait states. The CY7C1354DV25 and CY7C1356DV25
are equipped with the advanced (NoBL) logic required to enable
consecutive read and write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent write and
read transitions. The CY7C1354DV25 and CY7C1356DV25 are
pin compatible with and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BW_a–BW_d for CY7C1354DV25 and BW_a–BW_b for
CY7C1356DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. To avoid bus contention, the output
drivers are synchronously tri-stated during the data portion of a
write sequence. For best practices recommendations, please
refer to the Cypress application note System Design Guidelines
on www.cypress.com.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
200 MHz
166 MHz
Unit
2.8
3.2
3.5
ns
250
220
180
mA
40
40
40
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-48974 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 31, 2009
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