CY7C1354C_11 Datasheet, PDF (1/32 Pages) Cypress Semiconductor – 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture

CY7C1354C, CY7C1356C
9-Mbit (256 K × 36/512 K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■ Pin-compatible and functionally equivalent to ZBT
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 166 MHz
■ Internally self-timed output buffer control to eliminate the
need to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined
operation
■ Byte write capability
■ Single 3.3 V power supply (V_DD)
■ 3.3 V or 2.5 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 2.8 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in Pb-free 100-pin TQFP package, Pb-free, and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
The CY7C1354C and CY7C1356C^[1] are 3.3 V, 256 K x 36 and
512K x 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1354C and CY7C1356C are
equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred
on every clock cycle. This feature greatly improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1354C and CY7C1356C are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the clock enable (CEN) signal, which
when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the byte write selects
(BW_a–BW_d for CY7C1354C and BW_a–BW_b for CY7C1356C)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention,
the output drivers are synchronously tristated during the data
portion of a write sequence.
Logic Block Diagram – CY7C1354C (256 K × 36)
A0, A1, A
MODE
CLK
C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
S
E
N
S
E
MEMORY
ARRAY
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
Note
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05538 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 2, 2011
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