CY7C1354B Datasheet, PDF (1/29 Pages) Cypress Semiconductor – 9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

CY7C1354B
CY7C1356B
9-Mb (256K x 36/512K x 18) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined op-
eration
• Byte Write capability
• Separate V_DDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packag-
es
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354B and CY7C1356B are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354B and CY7C1356B are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW_a–BW_d for CY7C1354B and BW_a–BW_b for CY7C1356B)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1354B (256K x 36)
A0, A1, A
MODE
CLK
C
CEN
ADV/LD
BWa
BWb
BWc
BWd
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
S
E
N
S
E
MEMORY
ARRAY
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05114 Rev. *C
Revised June 16, 2004