CY7C1353G_12 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture

CY7C1353G
4-Mbit (256 K × 18) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■ Supports up to 100-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow-through operation
■ Byte write capability
■ 256 K × 18 common I/O architecture
■ 2.5 V / 3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 8.0 ns (for 100-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ Low standby power
Logic Block Diagram
Functional Description
The CY7C1353G is a 3.3 V, 256 K × 18 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 8.0 ns (100-MHz device).
Write operations are controlled by the two byte write select
(BW_[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
A0, A1, A
MODE
CLK
C
CE
CEN
ADV/LD
BWA
BWB
WE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
E
N
MEMORY
S
WRITE
ARRAY
E
DRIVERS
A
M
P
S
O
U
T
D
P
A
U
T
T
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
E
G
DQs
DQPA
DQPB
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
INPUT _E
REGISTER
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05515 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 25, 2012