CY7C1353G_07 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture

CY7C1353G
4-Mbit (256K x 18) Flow-through SRAM
with NoBL™ Architecture
Features
Functional Description^[1]
• Supports up to 133-MHz bus operations with zero wait
states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 18 common IO architecture
• 2.5V/3.3V IO power supply (V_DDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self timed writes
• Asynchronous Output Enable
• Available in Pb-free 100-Pin TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power
The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW_[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Logic Block Diagram
A0, A1, A
MODE
CLK
C
CE
CEN
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
E
N
MEMORY
S
WRITE
ARRAY
E
DRIVERS
A
M
P
S
O
U
T
D
P
A
U
T
T
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
E
G
DQs
DQPA
DQPB
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
INPUT _E
REGISTER
Note:
1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05515 Rev. *E
Revised July 09, 2007