CY7C1353B Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 256Kx18 Flow-Through SRAM with NoBL Architecture

353B
PRELIMINARY
CY7C1353B
256Kx18 Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z819 and MT55L256L18F
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 7.5 ns (for 117- MHz device)
— 8.5 ns (for 100-MHz device)
— 11.0 ns (for 66-MHz device)
— 12.0 ns (for 50-MHz device)
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
The CY7C1353B is a 3.3V, 256K by 18 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353B is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write-Read transitions. The
CY7C1353B is pin/functionally compatible to ZBT SRAMs
MCM63Z819 and MT55L256L18F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 7.5 ns (117-MHz de-
vice).
Write operations are controlled by the four Byte Write Select
(BWS_[1:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
ADV/LD
A_[17:0] ¹⁸
CEN
CCEE12
CE ₃
WE
BWS _[1:0]
Mode
CONTROL
and WRITE
LOGIC
CE
DaDta-In
Q
REG.
18
18
256KX18
18
MEMORY
18
ARRAY
DQ_[15:0]
DP_[1:0]
OE
Selection Guide
7C1353B-117 7C1353B-100 7C1353B-66 7C1353B-50 7C1353B-40
Maximum Access Time (ns)
7.5
8.5
11.0
12.0
14.0
Maximum Operating Current (mA) Commercial
375
350
250
200
175
Maximum CMOS Standby
Current (mA)
Commercial
5
5
5
5
5
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05266 Rev. **
Revised March 13, 2002