CY7C1353 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 256Kx18 Flow-Through SRAM with NoBL Architecture

1353
CY7C1353
256Kx18 Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z819 and MT55L256L18F
• Supports 66-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 11.0 ns (for 66-MHz device)
— 12.0 ns (for 50-MHz device)
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
The CY7C1353 is a 3.3V 256K by 18 Synchronous-
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency (NoBL™) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems
that require frequent Write-Read transitions.The CY7C1353 is
pin/functionally compatible to ZBT™ SRAMs MCM63Z819 and
MT55L256L18F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 9.0 ns (66-MHz de-
vice).
Write operations are controlled by the four Byte Write Select
(BWS_[1:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
ADV/LD
A_[17:0] ¹⁸
CEN
CE1
CE ₂
CE ₃
WE
BWS _[1:0]
Mode
CONTROL
and WRITE
LOGIC
CE
DaDta-In
Q
REG.
18
18
256KX18
18
MEMORY
18
ARRAY
DQ_[15:0]
DP_[1:0]
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
Commercial
NoBL is a trademark of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
7C1353-66
11
250 mA
5 mA
7C1353-50
12.0
200 mA
5 mA
7C1353-40
14.0
175 mA
5 mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 3, 1999