CY7C1350G_13 Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 4-Mbit (128 K x 36) Pipelined SRAM with NoBL™ Architecture

CY7C1350G
4-Mbit (128 K × 36) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Byte write capability
■ 128 K × 36 common I/O architecture
■ 3.3 V power supply (V_DD)
■ 2.5 V / 3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 2.8 ns (for 200-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable (OE)
■ Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option
Logic Block Diagram
Functional Description
The CY7C1350G is a 3.3 V, 128 K × 36 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1350G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 2.8 ns
(200-MHz device).
Write operations are controlled by the four byte write select
(BW_[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
S
E
N
S
E
MEMORY
ARRAY
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05524 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 25, 2013