CY7C1350B Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 128Kx36 Pipelined SRAM with NoBL Architecture

350B
PRELIMINARY
CY7C1350B
Features
128Kx36 Pipelined SRAM with NoBL™ Architecture
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices IDT71V546, MT55L128L36P, and MCM63Z736
• Supports 166-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 3.8 ns (for 150-MHz device)
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power (17.325 mW max.)
Logic Block Diagram
CLK
ADV/LD
A_[16:0] ¹⁷
CEN
CONTROL
CE1
and WRITE
CE2
LOGIC
CE3
17
WE
BWS_[3:0]
MODE
The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350B is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on ev-
ery clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1350B is pin/func-
tionally compatible to ZBT SRAMs IDT71V546,
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS_[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CE
DaDta-In
Q
REG.
36
36
128Kx36
36
MEMORY
ARRAY
36
DQ_[31:0]
DP_[3:0]
OE
.
Selection Guide
-166
-150
-143
-133
-100
-80
Maximum Access Time (ns)
3.5
3.8
4.0
4.2
5.0
7.0
Maximum Operating Current (mA)
Commercial
400
375
350
300
250
200
Maximum CMOS Standby Current (mA) Commercial
5
5
5
5
5
5
Shaded areas contain advance information.
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05045 Rev. **
Revised September 7, 2001