CY7C1347G_11 Datasheet, PDF (1/24 Pages) Cypress Semiconductor – 4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

CY7C1347G
4-Mbit (128 K × 36) Pipelined Sync SRAM
4-Mbit (128 K × 36) Pipelined Sync SRAM
Features
■ Fully registered inputs and outputs for pipelined operation
■ 128 K × 36 common I/O architecture
■ 3.3 V core power supply (V_DD)
■ 2.5- / 3.3-V I/O power supply (V_DDQ)
■ Fast clock to output times: 2.6 ns (for 250 MHz device)
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed writes
■ Asynchronous output enable
■ Offered in Pb-free 100-pin TQFP, Pb-free and non Pb-free
119-ball BGA package, and 165-ball FBGA package
■ “ZZ” sleep mode option and stop clock option
■ Available in Industrial and commercial temperature ranges
Functional Description
The CY7C1347G^[1] is a 3.3 V, 128 K × 36 synchronous pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic. CY7C1347G I/O pins can operate at
either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant
when V_DDQ = 2.5 V. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise is
2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium processor
or a linear burst sequence used by processors such as the
PowerPC. The burst sequence is selected through the MODE
pin. Accesses can be initiated by asserting either the address
strobe from processor (ADSP) or the address strobe from
controller (ADSC) at clock rise. Address advancement through
the burst sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the four Byte Write Select
(BW_[A:D]) inputs. A global write enable (GW) overrides all byte
write inputs and writes data to all four bytes. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous chip Selects (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To provide proper data
during depth expansion, OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
2.6
325
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
Unit
4.0
ns
225
mA
40
mA
Note
1. For best practice recommendations, refer to the Cypress application note, SRAM System Guidelines – AN1064.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05516 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 29, 2011
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