CY7C1347F Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 4-Mbit (128K x 36) Pipelined Sync SRAM

CY7C1347F
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
Functional Description^[1]
• Fully registered inputs and outputs for pipelined oper-
ation
• 128K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• User-selectable burst counter supporting Intel^
Pentium^ interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP, 119-pin BGA and
165-pin fBGA packages
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial temperature
ranges
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.
CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V
level, the I/O pins are 3.3V tolerant when V_DDQ = 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device)
CY7C1347F supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC^®. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW_[A:D]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2
A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD ,DQPD
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQD ,DQPD
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05213 Rev. *D
Revised April 9, 2004