CY7C1347B Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 128K x 36 Synchronous-Pipelined Cache RAM

1CY7C1347
CY7C1347B
128K x 36 Synchronous-Pipelined Cache RAM
Features
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined oper-
ation
• 128K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel Pen-
tium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial Temperature
ranges
Functional Description
The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined
cache SRAM designed to support zero-wait-state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A_[16:0]
17
GW
BWE
BW ₃
BW₂
BW₁
BW0
CE1
CE2
CE3
MODE
(A_[1;0]) 2
BURST ^Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
CE
D
REGISTER
15
D DQ[31:24], DP[3] Q
BYTEWRITE
REGISTERS
D DQ[23:16], DP[2] Q
BYTEWRITE
REGISTERS
D DQ[15:8], DP[1] Q
BYTEWRITE
REGISTERS
D DQ[7:0], DP[0] Q
BYTEWRITE
REGISTERS
D _{ENABLE CE} Q
REGISTER
The CY7C1347B I/O pins can operate at either the 2.5V or the
3.3V level, the I/O pins are 3.3V tolerant when V_DDQ = 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1347B supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW_[3:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
15
17
128KX36
MEMORY
ARRAY
36
36
D _{ENABLE DELAY} Q
REGISTER
OE
ZZ
SLEEP
CONTROL
Pentium and Intel are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
DQ_[31:0]
DP_[3:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 11, 2001