CY7C1346H Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 2-Mbit (64K x 36) Pipelined Sync SRAM

CY7C1346H
2-Mbit (64K x 36) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 64K × 36 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 3.5 ns (166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode Option
Logic Block Diagram
Functional Description^[1]
The CY7C1346H SRAM integrates 64K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn_{1tr)o, ldeinppthu-tesxp(AanDsSioCn,}
Chip Enables
ADSP, ^and
(CE₂ and _CE3), Burst
ADV), ^{Write Enables}
i(nBpWut^[s^A:Din^]c, laundde
BWE), ^{and Global}
the Output Enable
Write (GW).
(OE) and the
Asynchronous
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. _GW when active
LOW causes all bytes to be written.
The CY7C1346H operates from a +3.3V core power supply
while all outputs also operate with either a +3.3V/2.5V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
2
A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD,DQD
BYTE
WRITE REGISTER
DQC,DQPC
BYTE
WRITE REGISTER
DQB,DQPB
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
DQD ,DQPD
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE DRIVER
DQA,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05672 Rev. *B
Revised April 26, 2006
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