CY7C1345G_13 Datasheet, PDF (1/24 Pages) Cypress Semiconductor – 4-Mbit (128 K x 36) Flow-Through Sync SRAM

CY7C1345G
4-Mbit (128 K × 36) Flow-Through Sync SRAM
4-Mbit (128 K × 36) Flow through Sync SRAM
Features
■ 128 K × 36 common I/O
■ 3.3 V core power supply (V_DD)
■ 2.5 V or 3.3 V I/O supply (V_DDQ)
■ Fast clock-to-output times
❐ 8.0 ns (100 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed write
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ ZZ sleep mode option
Functional Description
The CY7C1345G is a 128 K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE₁), depth expansion
chip enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW_x, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
Selection Guide
Maximum access time
Maximum operating current
Maximum standby current
Description
100 MHz Unit
8.0
ns
205
mA
40
mA
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05517 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 25, 2013