CY7C1345G Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 4-Mbit (128K x 36) Flow-Through Sync SRAM

PRELIMINARY
CY7C1345G
4-Mbit (128K x 36) Flow-Through Sync SRAM
Features
• 128K X 36 common I/O
• 3.3V –5% and +10% core power supply (V_DD)
• 2.5V or 3.3V I/O supply (V_DDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Lead-Free 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode option
Functional Description^[1]
The CY7C1345G is a 131,072 x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn_{1tr)o, ldinepputhts-e(xApDaSnsCio,} nADCShPip,
Enables (CE₂ and _CE3),
and ADV), Write Enables
Burst
(BW_x,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable ^(OE) and the ZZ pin.
The CY7C1345G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1345G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
A[1:0]
BURST ^Q1
COUNTER
AND LOGIC
CLR
Q0
DQD, DQPD
BYTE
WRITE REGISTER
DQC, DQPC
BYTE
WRITE REGISTER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
DQD, DQPD
BYTE
WRITE REGISTER
DQC, DQPC
BYTE
WRITE REGISTER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05517 Rev. *A
Revised October 21, 2004