CY7C1345B Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 128K x 36 Synchronous Flow-Through 3.3V Cache RAM

CY7C1345B
128K x 36 Synchronous Flow-Through 3.3V Cache RAM
Features
Functional Description
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 36 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either
interleaved or linear burst sequence
• Separate processor and controller address strobes pro-
vide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V & 2.5V I/O levels
• ZZ “sleep” mode
The CY7C1345B is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1345B allows either interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A_[16:0]
17
GW
BWE
BWS₃
BWS₂
BWS₁
BWS₀
CE1
CE2
CE3
MODE
(A₀,A₁) 2
BURST ^Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
15
CE
D
REGISTER
15
DDQ[31:24],DP3Q
BYTEWRITE
REGISTERS
DDQ[23:16],DP2Q
BYTEWRITE
REGISTERS
D DQ[15:8],DP1 Q
BYTEWRITE
REGISTERS
D DQ[7:0],DP0 Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
17
128K X 36
MEMORY
ARRAY
36
36
OE
ZZ
SLEEP
CONTROL
INPUT
REGISTERS
CLK
DQ_[31:0]
DP_[3:0]
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Intel and Pentium are registered trademarks of Intel Corporation.
7C1345B-117
7.5
350
2.0
7C1345B-100
8.0
325
2.0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 11, 2000