CY7C1339G_12 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 4-Mbit (128 K × 32) Pipelined Sync SRAM

CY7C1339G
4-Mbit (128 K × 32) Pipelined Sync SRAM
4-Mbit (128 K × 32) Pipelined Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ 128 K × 32 common I/O architecture
■ 3.3 V core power supply (V_DD)
■ 2.5 V/3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1339G SRAM integrates 128 K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE₁), depth-expansion
chip enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW_[A:D], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW when active _LOW causes all
bytes to be written.
The CY7C1339G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
M ODE
ADV
CLK
A DSC
A DSP
BW D
BW C
BW B
BW A
BW E
GW
CE1
CE2
CE3
OE
ZZ
A DDR E SS
REGISTER
2
A [1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD
BYTE
W RITE REGISTER
DQC
BYTE
W RITE REGISTER
DQB
BYTE
W RITE REGISTER
DQA
BYTE
W RITE REGISTER
ENA BLE
REGISTER
PIPELINED
ENA BLE
DQD
BYTE
WRITE DRIVER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE DRIVER
DQA
BYTE
WRITE DRIVER
M EM ORY
ARRAY
SENSE
AM PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
INPUT
REGISTERS
SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05520 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 4, 2012