CY7C1339B Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 128K x 32 Synchronous Pipelined Cache RAM

CY7C1339B
128K x 32 Synchronous Pipelined Cache RAM
Features
• Supports 100-MHz bus for Pentium and PowerPC
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 128K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
• “ZZ” Sleep Mode and Stop Clock options
Functional Description
The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A_[16:0]
17
GW
BWE
BW ₃
BW₂
BW₁
BW0
CE1
CE2
CE3
MODE
(A_[1;0]) 2
BURST ^Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
CE
D
REGISTER
15
D DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D _DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
The CY7C1339B I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V-tolerant when V_DDQ = 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339B supports either the interleaved burst
sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the four Byte Write
Select (BW_[3:0]) inputs. A Global Write Enable (GW) overrides
all Byte Write inputs and writes data to all four bytes. All Writes
are conducted with on-chip synchronous self-timed Write
circuitry.
Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a Read cycle when emerging from a deselected
state.
15
17
128K × 32
MEMORY
ARRAY
32
32
D
Q
ENABLE DELAY
REGISTER
CLK
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ_[31:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05141 Rev. *A
Revised March 27, 2002