CY7C1334H Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture

CY7C1334H
2-Mbit (64K x 32) Pipelined SRAM with
NoBL™ Architecture
Features
Functional Description^[1]
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed write
• Asynchronous output enable (OE)
• Offered in Lead-Free JEDEC-standard 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
Logic Block Diagram
The CY7C1334H is a 3.3V/2.5V, 64K x 32
synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1334H is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of the SRAM, especially
in systems that require frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)
Write operations are controlled by the four Byte Write Select
(BW_[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
CLK
CEN
A0, A1, A
MODE
C
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
S
E
N
S
E
MEMORY
ARRAY
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05678 Rev. *B
Revised February 6, 2006
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