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CY7C133 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 2K x 16 Dual-Port Static RAM | |||
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CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
⢠True dual-ported memory cells which allow
simultaneous reads of the same memory location
⢠2K x 16 organization
⢠0.65-micron CMOS for optimum speed/power
⢠High-speed access: 25/35/55 ns
⢠Low operating power: ICC = 150 mA (typ.)
⢠Fully asynchronous operation
⢠Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
⢠BUSY output flag on CY7C133; BUSY input flag on
CY7C143
⢠Available in 68-pin PLCC
Logic Block Diagram
CEL
R/WLUB
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/WUB, R/WLB), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
CER
R/WRUB
R/WLLB
OEL
R/WRLB
OER
I/O8L â I/O15L
I/O0L â I/O7L
BUSYL[1]
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
CE L
OE L
R/WLUB
R/WLLB
ARBITRATION
LOGIC
(CY7C133 ONLY)
CER
OER
R/WRUB
R/WRLB
Note:
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
I/O8R â I/O15R
I/O0R â I/O7R
1[ ]
BUSYR
A10R
A0R
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose, CA 95134 ⢠408-943-2600
Document #: 38-06036 Rev. *B
Revised June 22, 2004
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