CY7C132_05 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 2K x 8 Dual-Port Static RAM

CY7C132/CY7C136
CY7C142/CY7C146
2K x 8 Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I_CC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits using slave CY7C142/CY7C146
• BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and
52-pin TQFP (CY7C136/146)
• Pb-Free packages available
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER
dual-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. On the PLCC
version, INT is an interrupt flag indicating that data has been
placed in a unique location (7FF for the left port and 7FE for
the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
R/W_L
CE_L
OE_L
I/O_7L
I/O_0L
BUSY_L^[1]
A _10L
A _0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
INT_L^[2]
CE_L
OE_L
R/W_L
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
CE_R
OE_R
R/W_R
Notes:
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
2. Open drain outputs; pull-up resistor required.
R/W_R
CE_R
OE_R
I/O_7R
I/O_0R
[1]
BUSY_R
A _10R
A _0R
[2]
INT_R
Pin Configuration
DIP
Top View
CE_L
R/W_L
BUSY_L
A_10L
OE_L
A_0L
A_1L
A_2L
A_3L
A_4L
A_5L
A_6L
A_7L
A_8L
A_9L
I/O_0L
I/O_1L
I/O_2L
I/O_3L
I/O_4L
I/O_5L
I/O_6L
I/O_7L
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12 _7C132 37
13 7C142 36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
V_CC
CE_R
R/W_R
BUSY_R
A_10R
OE_R
A_0R
A_1R
A_2R
A_3R
A_4R
A_5R
A_6R
A_7R
A_8R
A_9R
I/O_7R
I/O_6R
I/O_5R
I/O_4R
I/O_3R
I/O_2R
I/O_1R
I/O_0R
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06031 Rev. *C
Revised September 1, 2005