CY7C1328G_12 Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM

CY7C1328G
4-Mbit (256 K × 18)
Pipelined DCD Sync SRAM
4-Mbit (256 K × 18) Pipelined DCD Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double-cycle deselect)
❐ Depth expansion without wait state
■ 256 K × 18 common I/O architecture
■ 3.3 V core power supply (V_DD)
■ 3.3 V/2.5 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1328G SRAM integrates 256 K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE₁), depth-expansion
chip enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW_[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 5 and Truth Table on
page 8 for further details). Write cycles can be one to two bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing system
performance.
The CY7C1328G operates from a +3.3 V core power supply
while all outputs operate with a +3.3 V or a +2.5 V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz Unit
4.0
ns
225
mA
40
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05523 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 25, 2012