CY7C1327G_13 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – 4-Mbit (256 K x 18) Pipelined Sync SRAM

CY7C1327G
4-Mbit (256 K × 18) Pipelined Sync SRAM
4-Mbit (256 K × 18) Pipelined Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ 256 K × 18 common I/O Architecture
■ 3.3 V core power supply (V_DD)
■ 2.5 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 3.5 ns (for 166-MHz device)
■ Provide high performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Offered in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE₁), depth-expansion
chip enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW_[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as controlled
by the byte write control inputs. GW when active _LOW causes all
bytes to be written.
The CY7C1327G operates from a +3.3 V core power supply
while all outputs also operate with a +3.3 V or a +2.5 V supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE2
CE3
OE
ADDRESS
REGISTER
2 ^A[1:0]
BURST ^Q1
COUNTER AND
LOGIC
CLR
Q0
DQ B,DQP B
WRITE REGISTER
DQ A, DQP A
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ B,DQP B
WRITE DRIVER
DQ A, DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE
OUTPUT
AMPS
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05519 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 25, 2013