CY7C1327G Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 4-Mbit (256K x 18) Pipelined Sync SRAM

PRELIMINARY
CY7C1327G
4-Mbit (256K x 18) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 256K ×18 common I/O architecture
• 3.3V core power supply
• 3.3V / 2.5V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Lead-Free 100-pin TQFP and 119 Ball BGA packages.
• “ZZ” Sleep Mode Option
Logic Block Diagram
Functional Description^[1]
The CY7C1327G SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn_{1tr)o, ldeinppthu-tesxp(AanDsSioCn,}
Chip Enables
ADSP, ^and
(CE₂ and _CE3), Burst
ADV), ^{Write Enables}
i(nBpWut^[s^A:Bin^],claundde
BWE), ^{and Global}
the Output Enable
Write (GW).
(OE) and the
Asynchronous
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. _GW when active
LOW causes all bytes to be written.
The CY7C1327G operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 ^A[1:0]
BURST ^Q1
COUNTER AND
LOGIC
CLR
Q0
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05519 Rev. *A
Revised October 21, 2004